1) Field of the Invention
The present invention relates to a bus bridge and a data transfer method.
2) Description of the Related Art
Recently, an operation frequency of a central processing unit (CPU) on a bus line has been improved, and a data transfer speed between high-speed input/output (I/O) devices has also been improved. However, to ensure compatibility with older computer systems or for other purposes, it is necessary to connect a conventional low-speed I/O device to a computer system that includes a high-speed bus line.
Conventionally, a master device that is connected to a high-speed bus is connected to a bus bridge to access to a low-speed device. Through the bus bridge, the master device accesses to a low-speed device that is connected to a low-speed bus. Such a technology is disclosed in, for example, Japanese Patent Laid-Open Publication No. H10-4420. Moreover, in a conventional technology, a structure that includes a bus bridge to connect a Peripheral Component Interconnect (PCI) bus, which is a high-speed bus, and a low-speed bus is applied. The PCI bus is connected to a high-speed device and the low-speed bus is connected to a low-speed device, and the bus bridge is arranged therebetween. Such technology is disclosed in, for example, Japanese Patent Laid-Open Publication No. H11-110342. Furthermore, a technology that includes a structure in which a direct memory access (DMA) controller is arranged is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2001-109706. The structure includes a bus bridge, the DMA controller, a CPU (microprocessor), a high-speed I/O device, a low-speed I/O device, a high-speed bus, and a low-speed bus.
FIG. 7 is a timing chart of a conventional method to perform a read access to an I/O device on a low-speed bus line (hereinafter, a low-speed slave device) in a conventional system in which a computer system includes a high-speed bus line, and is connected a low-speed I/O device. In the conventional system, a bus master is arranged on a high-speed bus line (hereinafter, a high-speed bus master), and the bus master accesses to the low-speed slave device. In a following description, a side of the high-speed bus master is referred to as a host side, while a side of the low-speed slave device is referred to as an I/O side.
As shown in FIG. 7, the low-speed slave device generates a DMA request 1 toward a DMA controller (DMAC). Upon receiving the DMA request, the DMAC performs the read bus cycle 1 at the host side, which is shown with a reference numeral 2 in FIG. 7. A bus bridge performs the read bus cycle at the I/O side, which is shown with a reference numeral 3 in FIG. 7. When reading at the I/O side is completed, and the bus bridge sends a read data to the DMAC, the low-speed slave device generates a new DMA request 4 toward the DMAC.
The DMAC performs the read bus cycle 4 at the host side, which is shown with reference numeral 5 in FIG. 7. Also, the bus bridge performs the read bus cycle 4 at the I/O side, which is shown with a reference numeral 6 in FIG. 7. Then, the bus bridge sends a read data to the DMAC. Such a process is repeated to transfer a data. When the low-speed slave device generates a final DMA request 7, the DMAC and the bus bridge performs the final read bus cycle at the host side and the I/O side respectively, which are shown with reference numerals 8 and 9. When a final read data is sent from the bus bridge to the DMAC, the transfer of the data is finished.
However, if a low-speed I/O device is connected to a high-speed bus line, a large number of wait cycles are inserted when the low-speed I/O device is accessed. This may deteriorate the performance of the system. Moreover, if the high-speed I/O device and the low-speed I/O device are arranged on a same bus line, even a high-speed operation of the high-speed I/O device is inhibited because of the wait cycles that are inserted when the low-speed I/O device is accessed on the same bus line.